EETimes
April 18 2005
Startup proposes statistical yield modeling
Richard Goering
EE Times
(04/18/2005 12:17 PM EDT)
SANTA CRUZ, Calif. – Startup Ponte Solutions Inc. this week is
announcing its mission to bring statistical yield modeling into the
IC design flow. The company aims to solve one of the most vexing
problems design for manufacturablity (DFM) – getting accurate foundry
information into designer’s hands.
If foundries go along, Ponte’s encrypted models could end the reliance
on long lists of design rules and provide a much more accurate way of
calibrating designs for acceptable yields, according to Alex Alexanian,
president and CEO. Alexanian was formerly founder and CEO of SRAM
startup Mosaic Systems.
“Today the EDA world interfaces with the fab with design rules,”
Alexanian said. “We believe that’s going to change because of high
pain.” A 90 nm design rule deck might be over 1,000 pages, he noted,
including conflicting information.
Ponte Solutions is backed by $10 million in private investment
and venture capital, and employs 60, including 49 R&D engineers in
Alexanian’s native Armenia. The company promises a “platform” for
statistical yield modeling, a high-capacity data model, and yield
analysis tools, all to be released later in 2005.
Alexanian left Mosaic to start a company then called E-Z-CAD in
2001, starting with 27 people from Mosaic’s R&D center in Armenia.
Alexanian later succeeded in raising private funds, as well as funding
from Telos Venture Partners, U.S. Venture Partners, and Incubic.
He also built a team including two former directors of engineering from
Monterey Design Systems – Ara Markosian, CTO, and Sedrak Sargisian,
vice president of engineering. Arklin Kee, vice president of business
development, was a co-founder of Cadence. Nitin Deo, senior vice
president of marketing, recently left Magma Design Automation to
join Ponte.
Ponte is developing a “platform” for statistical yield modeling
that claims much better calibration with actual fab processes. It’s
based on a proprietary data model that Alexanian says can do “smart
processing on billions of polygons, hierarchical or flat, in hours
for large chips.”
Models will be encrypted, so that tools can use the information
but people outside the foundry can’t see it. Ponte expects that its
statistical yield information will be integrated into IC design tools.
Ponte’s Markosian explains how statistical yield modeling works in
an EEdesign exclusive feature.