Bad silicon ‘yields’ a DFM solution
by Richard Goering

Electronic Engineering Times
April 25, 2005

Santa Cruz, Calif. – A foundry’s “bizarre” mistake led Alex
Alexanian to start a company to help solve the toughest problem in
design-for-manufacturability (DFM): getting information that foundries
consider proprietary into designers’ hands.

Alexanian was chief executive officer of SRAM startup Mosaic Systems
when it received a 0.13-micron chip that was dead-on-arrival from
its foundry. Turned out the foundry forgot to put two metal layers
on the chip. That got Alexanian to thinking that perhaps there was a
“wrong setup” between design and manufacturing.

In 2001 he founded E-Z-CAD, now known as Ponte Solutions Inc., a
design-for-yield startup that this week will announce plans to bring
statistical yield modeling into the IC design flow. If foundries go
along, Ponte’s encrypted models could end the reliance on long lists
of design rules and provide a much more accurate way of calibrating
designs for acceptable yields.

Ponte is backed by $10 million in private investment and venture
capital, and employs 60, including 49 R&D engineers in Alexanian’s
native Armenia. The company promises a “platform” for statistical
yield modeling, a high-capacity data model and yield analysis tools,
all for release this year.

Alexanian is used to challenges. A graduate of the Faculty of Applied
Mathematics in Armenia, he worked on a programmable logic controller
project co-sponsored by the former Soviet Union and Great Britain.
When the USSR dissolved, so did the project, and Alexanian moved with
his family to California in 1994.

He worked at Cadence Design Systems Inc., where he was a member
of the consulting staff in the Silicon Ensemble group. In 1999 he
left to launch Mosaic Systems, which produced working silicon but is
no longer operating. Alexanian started E-Z-CAD with 27 people from
Mosaic’s R&D center in Armenia.

E-Z-CAD spurned an acquisition offer from HPL Technologies Inc. in
2002, which may have been fortuitous, given that HPL’s CEO was
charged a few months later with fabricating most of the company’s
revenue. Declining the offer meant Alexanian had to ask his team to
go without pay for four months.

They did. “That was the time we realized we really had a company,” he
said. Alexanian later succeeded in raising private funds, as well as
funding from Telos Venture Partners, U.S. Venture Partners and Incubic.

Alexanian is Ponte’s president and CEO. His team includes two former
directors of engineering from Monterey Design Systems-Ara Markosian,
Ponte’s CTO, and Sedrak Sargisian, its vice president of engineering.
Arklin Kee, vice president of business development, co-founded
Cadence. Nitin Deo, senior vice president of marketing, was with
Magma Design Automation.

There are many DFM startups today, but Ponte claims to have a
distinctive angle: its rejection of “binary” design rules in favor of
statistical yield models. “Today the EDA world interfaces with the fab
with design rules,” Alexanian said. “We believe that’s going to change
because of high pain.” A 90-nanometer design rule deck might be more
than 1,000 pages, he noted, and might include conflicting information.

Ponte is developing a platform for statistical yield modeling that
claims much better calibration with actual fab processes. These models
will include random defects such as particle contamination, systemic
defects such as etching and chemical-metal polishing violations,
and parametric effects from process variations.

Most important, they will be encrypted, so that tools can use the
information but people outside the foundry can’t see it. Ponte hopes
this will induce foundries to provide yield data they won’t release
today. While a generic description of failure mechanisms will be
public, foundry-specific parameters will not.

Getting foundry information is the biggest problem for DFM vendors,
said Gary Smith, chief EDA analyst at Gartner Dataquest. “The holy
grail is a secure process model, one that can be used by the DFM
vendors but can’t be reverse-engineered,” he said.

Ponte expects statistical yield information to be integrated into
design tools. For example, placement and routing tools can use the
models to do more yield-friendly wire spacing or install redundant
vias.

Underlying Ponte’s technology is a proprietary data model that can
do “smart processing on billions of polygons, hierarchical or flat,
in hours for large chips,” Alexanian said. It will support standard
interface formats so data can be exchanged with commercial EDA systems.